CSCI 355 Assignment 5,   Fall 1998

DUE:  

The assignment is due at the beginning of class, Wed  December 9. 


Read the paper "Automated Behavioural Testing of VHDL Components".

URL (html) http://malun1.mala.bc.ca:8080/~pwalsh/research/ccece96/full/main/main.html

URL (ps) http://malun1.mala.bc.ca:8080/~pwalsh/teaching/355/behavTest.ps

Your task is to model the controller in VHDL as a Mealy machine
(use JK edge triggered flip flops (from lab 8)).

Your model will be a structural description of the controller.  Verify
its behaviour using a testbench (same test bench as the previous
assignment).

INSTRUCTIONS

Hand in the following:

An overview of your design.
VHDL source file(s) (printout(s))
Test Plan.
VHDL test bench.
Floppy disk with your controller model and a simple users guide as to
how to compile and run your model.