CSCI 355 Assignment 3,   Fall 1998

DUE:  

The assignment is due at the beginning of class, Wed  November 25. 

QUESTIONS (from the class text):

Page 254	Question 1
Page 254	Question 12
Page 257	Question 13
Page 257	Question 14
Page 258	Question 15
Page 563	Question 5
Page 565	Question 8
Page 566	Question 15
Page 567	Question 16

Where you are asked to develop a VHDL model, you must also develop a
test plan and  a testbench to verify the behaviour of your model. You
must had in your VHDL listings and be prepared to demonstrate the
behaviour of your model to the instructor if asked to do so.

INSTRUCTIONS:

Answer all the questions listed above.  Label each of your solutions
clearly. You will not get any credit for work that is poorly described.
The onus is on you to convince me that your solutions are well thought
out and correct.