Notices:

• comp.lang.vhdl

• CAD Tools
  • Cew for C++
  • HC11 download procedure (from 261)
  • xcircuit
  • xcircuit tutorial
  • ise 6 Quick-Start Tutorial

• Manuals
  • XSA-50 Manual (Xess)
  • Labs
    • Intro (Last modified:12/09/13 13:45
    • Lab2 (Last modified:23/09/13 20:05
    • Lab3 (Last modified:09/10/13 17:17
    • Lab4 (Last modified:30/10/13 16.23
    • Lab6 (Last modified:06/11/13 10.50
    • Lab7 (Last modified:13/11/13 10.05
    • Lab8 (Last modified:13/11/13 16.05
    • Labs9 (Last modified:15/11/13 15.30

    • App-Lab3

    • Lab0 BB photo
    • Pin-Out Sheet Template

• Mini Project
  • Mini Proj Part A

• Hamming Code
• VLSI Programmable Logic Devices
• FPGA and CPLD Architectures: A Tutorial
• Writing VHDL for RTL Synthesis
• Active VHDL from Aldec
• Active VHDL Application Notes (select How-To Guide)

• Green Mountain Local Docs (plus tutorial)

• ASSP Support Page for VHDL

• Contempory Logic Design (on-line text)
• Application Specific Integrated Circuits (on-line text)

• Partial TTL Data Book
• TTL Reference Material

• Past Midterm Exams
  • Midterm Exam 02

• Past Final Exams
  • Final Exam Dec 98
  • Final Exam Dec 99
  • Final Exam Dec 00
  • Final Exam Dec 02
  • Final Exam Dec 03
  • Final Exam Dec 05
  • Final Exam Dec 06
  • Final Exam Dec 07