LAB # 2

OBJECTIVES
After completing this experiment, you will be able to: Understand the concept of Hierarchical structures. Construct a reasonably complicated circuit using the DDE breadboard.

MATERIALS NEEDED
DDE; 7486 XOR IC; 7408 AND IC; 7432 OR IC; logic probe

Consider the following:

entity HALF_ADDER is
	port (A, B : in BIT; S, C : out BIT);
end entity HALF_ADDER;

architecture STRUCTURE of HALF_ADDER is

	component XOR_2
		port (A, B : in BIT; Z : out BIT);
	end component XOR_2;

	component AND_2
		port (A, B : in BIT; Z : out BIT);
	end component AND_2;

begin
	XR1: XOR_2 port map (A, B, S);
	A1: AND_2 port map (A, B, C);
end architecture STRUCTURE;

entity FULL_ADDER is
	port (D1, D2, Cin : in BIT; Sum, Cout : out BIT);
end entity FULL_ADDER;


architecture STRUCTURE of FULL_ADDER is

	signal HA1_SUM, HA1_CARRY, HA2_CARRY : bit;

	component OR_2
		port (A, B : in BIT; Z : out BIT);
	end component OR_2;

	component HALF_ADDER 
		port (A, B : in BIT; S, C : out BIT);
	end component HALF_ADDER;

begin
	HA1: HALF_ADDER port map (D1, D2, HA1_SUM, HA1_CARRY);
	HA2: HALF_ADDER port map (HA1_SUM, Cin, Sum, HA2_CARRY);
	OR1: OR_2 port map (HA1_CARRY, HA2_CARRY, Cout);
end architecture STRUCTURE;